The invention relates to a method of fabricating an integrated circuit in a microelectronic device or MEMS (micro-electromechanical) device. More particularly, the present invention is directed to the method of trimming the linewidth of photoresist which translates after etch transfer to shorter gate lengths in MOS transistors.
One of the key steps in the manufacture of a Metal-oxide-semiconductor field effect transistor (MOSFET) is formation of a polysilicon or metal gate. The width of the gate conducting metal is typically one of the smallest dimensions in the device. To satisfy a constant demand for higher performance devices, the gate length or critical dimension (CD) which is actually measured as the width of a metal line is continually being reduced in each successive technology generation. For the 100 nm technology node that is currently being implemented in manufacturing, gate lengths as small as 60 or 70 nm are being produced. One shortcoming of state of the art lithography processes is that they are incapable of controllably printing features in photoresist smaller than about 100 nm. Many semiconductor manufacturers have overcome this problem using a trimming process which laterally shrinks the photoresist line with an etch step.
MOSFETs are typically made by first defining active areas in the substrate by forming isolation regions consisting of insulating material like silicon dioxide. The isolation regions can be generated by local oxidation of silicon (LOCOS) or by a shallow trench isolation (STI) technique. A gate oxide layer is grown over the substrate between the isolation regions. Then a gate electrode material such as polysilicon is deposited and patterned above the gate oxide layer. The gate length is determined by initially patterning a photoresist layer on the gate electrode layer. The openings in the photoresist are transferred through the gate layer by means of a plasma etch. Then ion implantation is used to form source/drain regions which define a channel length under the gate oxide. The final steps in making the device consist of adding sidewall spacers adjacent to the gate electrode, depositing an insulating layer on the substrate and forming contacts to the source/drain regions and to the gate electrodes.
The photoresist material which is patternwise exposed through a reticle can be either positive or negative tone. A positive tone photoresist undergoes a reaction in exposed regions that renders them soluble in a developing solution which is normally aqueous tetrabutyl ammonium hydroxide. Unexposed portions of the photoresist film remain insoluble in the developer. In negative photoresist, exposed regions are crosslinked or become otherwise insoluble in developer while the unexposed portions are washed away in aqueous base solution. Photoresist can be applied as a single layer material or part of a bilayer system. In bilayer applications, the pattern formed in a thin imaging layer is etch transferred through a thicker underlayer that is used for its planarization and anti-reflective properties. In some cases, a single layer photoresist is selected which is very opaque to the incident exposing radiation such that only a top portion near the surface absorbs energy that causes a chemical change to occur. Top surface imaging techniques are frequently combined with a silylation process which forms Oxe2x80x94Si bonds selectively in either the exposed or unexposed regions. A subsequent oxygen etch removes photoresist in regions that are not protected by the Oxe2x80x94Si bonds in the film. Thermal stability of photoresist features are typically in the range of 90xc2x0 C. to 150xc2x0 C. Any processes including plasma etches that involve temperatures in this range or above the thermal stability limit will cause the resist to flow and distort.
The lithography process used to pattern the photoresist above the gate layer generally involves exposure tools which use wavelengths that are selected from a range of 450 nm to sub-200 nm. High throughput projection electron beam tools that have the capability of imaging 50 to 70 nm resist features are still in development and are too expensive to implement. X-ray and ion beam imaging systems have also been used to image photoresist but in general are not found in high volume manufacturing lines. Even with the most advanced exposures tools, phase shift reticles, and resolution enhancement techniques that are currently available in manufacturing, the minimum feature size that can be reliably imaged in a photoresist is about 100 nm. This size is not small enough to meet the demand for sub-100 nm gate lengths for most new devices. As a result, the industry has resorted to other methods that require trimming the pattern in the masking layer that is subsequently etch transferred to form the gate electrode.
The process of accurately and repeatedly etching patterns has been the subject of significant development, especially in the area of semiconductor electronics. The extent to which integrated circuits can be miniaturized depends on the accuracy and reliability of the patterning and etching processes. The etching process involves the use of a mask to selectively allow an etchant to remove underlying semiconductor or conductive material that has been exposed through openings in the mask pattern. Although wet etchants can be employed, a dry plasma etch is usually preferred when the mask is a patterned photoresist layer.
One of the original methods of MOS device fabrication involving gate lengths less than 200 nm is published in IEEE Electron Device Letters, Vol. 9, No. 4, pp. 186-188 (1988) by C. Hu. A plasma etching system with an O2 pressure of 300 mTorr and RF power of 50 Watts was used to laterally trim a photoresist feature before an etch transfer into an underlying polysilicon layer. Oxygen radicals react with elements of C, H, N, and S in the photoresist to form their corresponding oxides such as CO2, H2O, NO2 and SO2 which are swept away in the exhaust stream.
A more recent publication by M. Ono in J. Vacuum. Sci. Tech. B, Vol. 13, 1740-1743 (1995) mentions the use of oxygen plasma ashing to achieve 40 nm gate electrodes. The lateral trimming is about 15 nm/min. and is almost independent of the original photoresist dimension which varies from 216 to 324 nm in width.
Besides the lateral erosion of the photoresist image, some top loss can also occur during the trimming process which is unacceptable if there is not enough resist thickness remaining to serve as a mask for the subsequent etch into the polysilicon layer. The vertical trim rate of a photoresist image can be more than twice as fast as the horizontal trim rate. Jeon et al. in J. Vacuum Science Tech. B, Vol. 12, pp., 2800-2804 (1994), utilize a Deep Ultraviolet (UV) hardening with wavelengths near 300 nm to harden the photoresist after a trimming step and then proceed with etch transfer into an underlying hard mask. The hard mask (silicon nitride) then becomes a mask for etching polysilicon gates. The photoresist in this example is patterned with i-line (365 nm) imaging and contains novolac resin which becomes crosslinked in the hardening mechanism. However, other resists such as those imaged by Deep UV (248 nm) radiation which contain polyvinyl phenol polymers can be crosslinked or hardened as well. The particular wavelengths selected for hardening depend on their absorbance in the photoresist film. A high absorbance will cause a hardening in only the outer skin while a low absorbance will result in too little energy being absorbed by the film and an excessively prolonged hardening process.
In some cases a bottom anti-reflective coating (BARC) is formed on the gate layer prior to the photoresist coating in order to control reflectivity during the photoresist patterning process. This leads to a tighter control of dimensions in the printed pattern. In U.S. Pat. No. 5,804,088, a TiN BARC also functions as a hard mask for the polysilicon etch step. U.S. Pat. No. 6,010,829 describes the use of an organic BARC which is isotropically etched with the photoresist at a 1:1 selectivity. However, BARC layers require extra coating and removal steps that add cost to the manufacturing process. Organic BARC can be difficult to rework and strip since it is generally cured over 200xc2x0 C.
Other trimming methods found in U.S. Pat. Nos. 5,866,473 and 5,776,821 involve forming an oxide layer on the vertical walls of an etched polysilicon gate. Oxide formation consumes some of the polysilicon and when the oxide is removed the polysilicon gate has a smaller dimension. Again, the formation of an extra layer requires additional formation and removal processes that can add to the overall cost of the device. Preferably, any trimming process can be done with existing materials and equipment to minimize device cost.
Another photoresist hardening method which allows more photoresist thickness to be retained during the etch steps is described in U.S. Pat. Nos. 5,876,903 and 6,232,048. Bombardment with ionized particles with energies of 20 to 100 keV hardens the surface of the photoresist and makes is more resistant to plasma etch. One drawback is that the ion energy and high dose have a tendency to damage the substrate which cannot be easily annealed since the gate is sensitive to high temperatures.
Therefore, an improved photoresist trimming process is needed whereby the vertical etch rate is slowed to allow a significant retention of film thickness that will provide a good mask for the polysilicon etch step while the horizontal process is slowed to allow a good control of the resulting feature size. The process should ideally avoid the formation of extra layers that require additional process steps and add cost to the device.
The present invention is a method of preparing reduced photoresist linewidth dimensions during the fabrication of integrated circuits for semiconductor devices, micro-electromechanical (MEMS) devices, or other devices that require the formation of patterned features on a substrate.
One objective of the present invention is to provide a means of reducing the linewidth of a photoresist pattern that is used to define a gate length of a gate electrode in a MOSFET device. The lateral trimming of a photoresist feature should be slow enough to allow the reduced feature size to be formed in a controlled and reproducible manner. Preferably, the vertical trimming of the photoresist will be slowed as well to provide enough thickness retention that allows the photoresist to serve as an effective mask during a subsequent etch transfer of the pattern into the underlying substrate.
A further objective of the present invention is to provide a method of reducing the linewidth of a photoresist pattern that does not involve the formation of extra layers or use of new tools that can add to the cost of manufacturing the device.
A still further objective of the present invention is to provide a method of reducing the linewidth or increasing the space width of a photoresist pattern that is subsequently etch transferred through an underlying layer or substrate. The pattern is not restricted to an isolated line but can consist of dense lines and spaces, contact holes, trenches or other commonly used photoresist features.
These objectives are achieved by providing a patterned photoresist layer on a substrate. The photoresist may be positive or negative tone and can be imaged with a variety of radiation sources including electron beam, ultraviolet sources that have a wavelength or wavelengths selected from a range of about 450 nm to below 200 nm, and X-ray sources. The photoresist is selected from a group of materials including single layer photoresist, bilayer imaging systems, or top surface imaging systems.
In one embodiment, the width of the photoresist profile is controllably reduced by cooling the substrate to less than 20xc2x0 C. while etching in a high density oxygen and argon based plasma. The method further makes use of a low pressure inductively coupled plasma (ICP) wherein the ICP coil power is applied to create a remote high density oxygen and argon rich plasma. The plasma also forms an intense ultraviolet radiation which simultaneously hardens the outer portions of the resist feature while the plasma etches away the photoresist in vertical and horizontal directions. The combination of slow etch rate and UV hardening reduces the vertical etch rate so that an adequate thickness of photoresist is retained to serve as an etch mask for a subsequent etch transfer step into the underlying substrate which is preferably polysilicon. The lateral etch rate is slower than the vertical rate and is in the range of 150 to 200 Angstroms per minute for features smaller than 1 micron in width. This method has been successfully implemented to trim a photoresist line having a 1.2 micron width to one that is only 0.08 microns or 80 nm with vertical sidewalls. The photoresist pattern with reduced linewidth is then etched transferred in an anisotropic manner into an underlying substrate such as polysilicon during the fabrication of a MOSFET device. Any remaining photoresist is stripped by conventional methods.
As an alternative, a UV hardening process is performed prior to the trimming step. A commercially available flood exposure system can be used to apply radiation with selected bandwidths from the 220 to 400 nm range, depending upon the lamp and filter set. Normally, a one to four minute exposure is combined with a thermal treatment of from 100xc2x0 C. to 240xc2x0 C. and is sufficient to harden the outer surface of the photoresist feature. The substrate is then subjected to the plasma etch process described in the first embodiment.
In a second embodiment, the photoresist pattern is formed on a substrate or on a hard mask over a substrate as depicted in FIGS. 2a-2c. A space width in a photoresist feature which can be a combination of lines and spaces, contact holes, or trenches becomes larger as the lateral etch from the plasma reduces the photoresist dimension. Simultaneous UV hardening and high density etch in an ICP chamber with oxygen and argon plasma enables a slow etch that minimizes a vertical loss of photoresist while controlling the horizontal component.
The advantages of the embodiments of this invention are that vertical and horizontal etch rates during a photoresist trimming process are controlled. No extra coatings are required. Since the etch and UV hardening can take place in the same chamber, a high throughput process is possible. Furthermore, the low temperature process does not distort the photoresist image.